Index

Lecture 01

System Verilog

1. Introduction

Gate-Level Modelling

e.g.

01-01

01-01

e.g. Full adder (1-bit)

01-02

01-02

\(c_{in}\) \(a\) \(b\) \(c_{out}\) \(sum\)
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

\(sum=a\oplus b\oplus c\)

\(c_{out}=(a\oplus b)\cdot c_{in}+a\cdot b\)

full_adder_gates.sv
module full_adder(output c_{out}, sum,
                  input  c_{in}, a, b);
    // instances of primitives, not function calls
    wire w1, w2, w3;
    xor  x1(w1, a,b);
    xor  x2(sum, c_in, w1);
    and  a1(w2, a, b);
    and  a2(w3, w1, c_in);
    or   o1(c_out, w3, w2);
endmodule
full_adder_tb.sv
module full_adder_tb;    //no port list
    reg  carry_in, x, y; //remember value until next assignment
    wire carry_out, z;
    full_adder dut(.c_out(carry_out), .sum(z), .c_in(carry_in), .a(x), .b(y)); //named post list
    
    // procedure block: statements are evaluated sequentially
    initial begin   //run once at t=0
        carry_in=0;
        x=0;
        y=0;
        #10 x=1;    //delay for 10 time units 
        #10 y=1;    
        #10 carry_in=1;
        #10 $stop;  // $ sign is for system task
    end

    // dump signal traces, 0 = all levels of hierarchy
    initial $dumpvars(0, full_adder_tb); 
endmodule

Index