Index

# Lecture 01

## 1. Introduction

• Hardware description languages: VHDL, System Verilog (was Verilog until 2005), Systeml
• Can be used to:
• simulate digital circuit designs
• synthesize to an integrated circuit or programmable logic

### Gate-Level Modelling

• predefined primitives (gates): and, nand, or, nor, xor, xnor
• signal values: 0, 1, x(unknown), z(high impedence)
• System Verilog is case sensitive except for x and z

e.g.

$$c_{in}$$ $$a$$ $$b$$ $$c_{out}$$ $$sum$$
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

$$sum=a\oplus b\oplus c$$

$$c_{out}=(a\oplus b)\cdot c_{in}+a\cdot b$$

module full_adder(output c_{out}, sum,
input  c_{in}, a, b);
// instances of primitives, not function calls
wire w1, w2, w3;
xor  x1(w1, a,b);
xor  x2(sum, c_in, w1);
and  a1(w2, a, b);
and  a2(w3, w1, c_in);
or   o1(c_out, w3, w2);
endmodule
• testbench:
• instantiate the design module and simulate inputs to verify functional correctness (and timing)
full_adder_tb.sv
reg  carry_in, x, y; //remember value until next assignment
wire carry_out, z;
full_adder dut(.c_out(carry_out), .sum(z), .c_in(carry_in), .a(x), .b(y)); //named post list

// procedure block: statements are evaluated sequentially
initial begin   //run once at t=0
carry_in=0;
x=0;
y=0;
#10 x=1;    //delay for 10 time units
#10 y=1;
#10 carry_in=1;
#10 $stop; //$ sign is for system task
end

// dump signal traces, 0 = all levels of hierarchy
endmodule